1. Field of the Invention
The present invention relates to an antifuse-based field programmable gate array (FPGA). More particularly, the present invention relates to a partitioned architecture for a high density antifuse based FPGA.
2. The Prior Art
As is well understood by those of ordinary skill in the art, the architecture for an antifuse based FPGA typically includes logic modules which may be configured as logic gates that are connected together to form higher logic functions. The logic modules are connected together by routing conductors, and the connections are made by programming antifuses. As the number of gates included in an antifuse based FPGA increases, there are a number of considerations which place constraints on the size of the FPGA.
As a first consideration, there is a limit on the number of antifuses that are permitted on any given routing conductor due to the amount of leakage current through and the resistive load across unprogrammed antifuses during programming. As a second consideration, due to the capacitive coupling between routing conductors in the FPGA, there is a limit on the amount of peak current that can pass through an antifuse during normal operations. Since the peak current is a function of the programming current which decreases as processes shrink, long capacitive nets of routing conductors with antifuses on them are limited as to the amount of current which they can charge and discharge.
Further, the total fuse leakage during the normal operation of a large antifuse based FPGA can also be quite considerable. It is well understood that the amount of leakage current is a function of the supply voltage and the junction temperatures. For example, a single fuse having a 3.6 volt supply can leak about approximately 5 nano amperes of current at 125xc2x0 C. As a consequence, in a 10K gate array having approximately 1 million antifuses, a standby current of 5 milliamps is generated, and for a 200K gate array, a standby current of 100 milliamps is possible.
Finally, for large antifuse based arrays, the programming time of the FPGA can also become prohibitively long, having a duration, for example, of up to four hours to program a 50K FPGA, and up to ten hours to program a 200K gate FPGA.
It is, therefore, an object of the present invention to reduce the capacitive coupling between tracks in a large antifuse based FPGA.
It is a further object of the present invention to reduce the programming time in a large antifuse based FPGA.
It is a further object of the present invention to reduce the standby current in a large antifuse based FPGA.
It is yet another object of the present invention to implement an antifuse based architecture for a large FPGA that is repeatable so that it may be scaled to larger arrays.
It is yet another object of the present invention to provide a partitioned antifuse based FPGA.
It is a further object of the present invention to provide a partitioned FPGA with fixed and segmented interconnect routing channels for minimal and predictable routing delay.
According to the present invention an antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. Further, by employing repeatable blocks, the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable blocks are interface buffers for connecting to adjacent blocks and to an interconnect matrix that is connectable blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.
As a further aspect of the present invention, each of the repeatable blocks may have a separate Vpp. Once programming is completed, these separate Vpp""s can be employed as separate Vcc""s for each of the repeatable blocks so that the voltage level to a particular block can be lowered to minimize standby current when the inputs and outputs of that particular block are not switching.